The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device including an input/output sense amplifier that amplifies a read data and provide it to the external, when making a read operation.
In general, data stored in a memory cell of a semiconductor memory device is transferred to an input/output sense amplifier via any one of a pair of local input/output lines when a read command is inputted in a read operation.
And, the transferred data is amplified by the input/output sense amplifier and then outputted via a global input/output line.
A semiconductor memory device may have a structure of two banks that are arranged symmetrically to each other with respect to the input/output sense amplifier arranged therebetween the two banks. When the data stored in one of the above two banks is transferred to the global input/output line in a read operation, the input/output sense amplifier for the remaining bank should remain floating with the global input/output line.
FIG. 1 shows one example of a graphic memory structure divided into four quarters. In one quarter (e.g., upper left quarter of FIG. 1), eight banks BA0 to BA7 are arranged such that one set of four banks BA0, BA2, BA4, BA6 and the other set of four banks BA1, BA3, BA5, BA7 are laid out symmetrically to each other with one-to-one relation between each symmetrically arranged banks. An input/output sense amplifying circuit IOSA is arranged therebetween the two sets of banks. Another set of eight banks DQ0 to DQ7 is also arranged in the same upper left corner of FIG. 1. The input/output sense amplifier disposed between the two banks BA0 and BA1 can be represented as shown in FIG. 2.
Referring to FIG. 2, two input/output sense amplifiers 10, 20 are shown therein. The input/output sense amplifier 10 corresponds to the bank BA0, and the input/output sense amplifier 20 corresponds to the bank BA1. Both input/output sense amplifiers 10, 20 are connected to a global input/output line RGIO. Each input/output sense amplifiers 10, 20 comprises sense amplifiers 11, 21, inverters IV1, IV2, and drivers 12, 22, respectively.
With such structure, to read data stored in the bank BA0, the data stored in the bank BA0 is transferred to the sense amplifier 11 via any one of a pair of local input/output lines LIO0 and LIO0B, the sense amplifier 11 is turned-on by a strobe signal IOSA_STROBE0 to amplify the inputted data and outputs an amplified signal D0 and an inverted amplified signal D0B.
And, the inverted amplified signal DOB is inverted by the inverter IV1, and as the amplified signal D0 and the signal inverted by the inverter IV1 are inputted to the driver 12, the driver is turned-on to transfer a high or low level of data to the global input/output line RGIO. After this, the data transferred to the global input/output line RGIO is latched through a latch LAT.
While the bank BA0 is accessed to read data, the sense amplifier 21 is turned-off by the strobe signal IOSA_STROBE0, and the driver 22 is turned-off by the amplified signal D1 and the output signal of the inverter IV2 to allow the output stages of the global input/output line RGIO and the driver 22 to be floated.
It is noted that all banks BA0 to BA7 commonly use the global input/output line RGIO. When reading the bank BA0, for example, the output stage of the global input/output line RGIO and the driver 22 are floated, in order to prevent the influence from the input/output sense amplifiers of the remaining banks (such as BA1 to BA7) on the data that is read from a specific bank (such as BA0).
In other word, as shown in FIG. 3, when reading the bank BA0, only the driver 12 of the BA0 is turned-on and the drivers corresponding to the remaining banks BA1 to BA7 are floated together with the global input/output line RGIO so that all the drivers corresponding to the remaining banks BA1 to BA7 have no effect on the operation of reading the bank BA0.
However, when all drivers for the banks BA0 to BA7 are commonly connected to the global input/output line as shown in FIG. 3, a junction loading can occur due to the remaining seven drivers of BA1 to BA7 (besides the driver 12 corresponding to the bank BA0) causing deterioration of the slop of the data carried by the global input/output line RGIO.
When the slop of the data carried on the global input/output line RGIO is deteriorated, the time ‘tAA’ required for inputting the command and then outputting the data increases, thereby causing problems of decreased operating speed of the memory device.
Also, as the drivers included in the respective sense amplifier generally drive the long global input/output line RGIO, the size of each driver is rather large. When the large-sized drivers are disposed in every bank of BA0 to BA7 as shown in FIG. 3, the layout area required for the drivers in the semiconductor memory device becomes a serious problem.